
2010 Microchip Technology Inc.
DS39774D-page 13
PIC18F85J11 FAMILY
FIGURE 1-2:
PIC18F8XJ11 (80-PIN) BLOCK DIAGRAM
PRODL
PRODH
8 x 8 Multiply
8
BITOP
8
ALU<8>
8
3
W
8
Instruction
Decode &
Control
Data Latch
Data Memory
(3.9 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH
PCL
PCLATH
8
31 Level Stack
Program Counter
Address Latch
Program Memory
(128 Kbytes)
Data Latch
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
ROM Latch
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank
State Machine
Control Signals
Decode
S
yste
m
B
u
s
In
ter
face
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7(1,2)
RC0:RC7(1)
RD0:RD7(1)
RE0:RE7(1)
RF1:RF7(1)
RG0:RG4(1)
PORTB
RB0:RB7(1)
PORTH
RH0:RH7(1)
PORTJ
RJ0:RJ7(1)
AUSART
Comparators
MSSP
Timer2
Timer1
Timer3
Timer0
CCP1
ADC
10-Bit
EUSART
CCP2
OSC1/CLKI
OSC2/CLKO
VDD,VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Precision
Reference
Band Gap
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Timing
Generation
INTRC
Oscillator
8 MHz
Oscillator
BOR and
LVD(3)
Note 1:
2:
information
3:
Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.